
module DE10_LITE(

	//////////// CLOCK //////////
	input 		          		ADC_CLK_10,
	input 		          		MAX10_CLK1_50,

	//////////// SDRAM //////////
	output		    [12:0]		DRAM_ADDR,
	output		     [1:0]		DRAM_BA,
	output		          		DRAM_CAS_N,
	output		          		DRAM_CKE,
	output		          		DRAM_CLK,
	output		          		DRAM_CS_N,
	inout 		    [15:0]		DRAM_DQ,
	output		          		DRAM_LDQM,
	output		          		DRAM_RAS_N,
	output		          		DRAM_UDQM,
	output		          		DRAM_WE_N,

	//////////// KEY //////////
	input 		     [1:0]		KEY,

	//////////// LED //////////
	output		     [9:0]		LEDR,

	//////////// SW //////////
	input 		     [9:0]		SW
);




wire [24:0] ADDRESS;// {BA,行，列}

wire reset;
reg [27:0] reset_release = 28'h0000_0000;

wire 	[15:0] DATA_READ;
reg 	[15:0] DATA_WRITE;

reg [24:0] ADDR_COUNTER_WRITE = 25'd0;
reg [24:0] ADDR_COUNTER_READ = 25'd0;

wire clk_c0;//100MHZ
wire clk_c1;//100MHZ-3ns
wire clk_c2;//

reg write_pulse=1'b0;
reg read_pulse=1'b0;


pll pll1(
	.areset(),
	.inclk0(MAX10_CLK1_50),
	.c0(clk_c0),
	.c1(clk_c1),
	.c2(clk_c2)
);
	
debouncer debouncer_KEY0( //按键消抖
	.slow_clk(clk_c2),
	.btn_in(KEY[0]),
	.btn_out(KEY_0)
);
	
debouncer debouncer_KEY1(
	.slow_clk(clk_c2),
	.btn_in(KEY[1]),
	.btn_out(KEY_1)
);

sdram_controller(
			.RE(read_pulse),
			.WR(write_pulse),
			.ADDR(ADDRESS),
			.RD_REQUEST_APPROVED(RD_REQUEST_APPROVED),
			.WR_REQUEST_APPROVED(WR_REQUEST_APPROVED),
	  		.RD_DATA(DATA_READ),
			.WR_DATA(DATA_WRITE),
			.MAX10_CLK1_100(clk_c0),
	 		.MAX10_CLK2_100_3ns(clk_c1),
			.DRAM_ADDR(DRAM_ADDR),
		   .DRAM_BA(DRAM_BA),
		   .DRAM_CAS_N(DRAM_CAS_N),
		   .DRAM_CKE(DRAM_CKE),
		   .DRAM_CLK(DRAM_CLK),
	      .DRAM_CS_N(DRAM_CS_N),
			.DRAM_DQ(DRAM_DQ),
	      .DRAM_LDQM(DRAM_LDQM),
	      .DRAM_RAS_N(DRAM_RAS_N),
	      .DRAM_UDQM(DRAM_UDQM),
	      .DRAM_WE_N(DRAM_WE_N),
			.reset_n(reset)
);


// 上电复位
always @ (posedge clk_c0)
begin
	if(reset_release<28'h1DCD6500)//2s
		reset_release<=reset_release+1;
	
end
assign reset=(reset_release==28'h1DCD6500)?1:0;

//读写地址为0
assign ADDRESS=(write_pulse==1)?ADDR_COUNTER_WRITE:ADDR_COUNTER_READ;
assign LEDR = DATA_READ[9:0];

/////////////////////读
integer sm_read_state=0;
	
always @ (posedge MAX10_CLK1_50)
begin
	if(reset==1'b1 & KEY_0==1'b1 & sm_read_state==0) begin
			read_pulse = 1'b1;
			sm_read_state = 1;
	end
	else if (sm_read_state==1)	begin
			sm_read_state = 2;
	end
		
	else if(sm_read_state==2) begin
			sm_read_state = 3;
	end
	else if(sm_read_state==3) begin
			if(RD_REQUEST_APPROVED) begin
				read_pulse = 1'b0;
				sm_read_state = 4;
			end 
	end
	else if(sm_read_state==4) begin
			if(!WR_REQUEST_APPROVED) begin
				sm_read_state = 0;
			end
	end
end



/////////////////////写
integer sm_write_state=0;

always @ (posedge MAX10_CLK1_50)
begin
	if(reset==1'b1 & KEY_1==1'b1 & sm_write_state==0) begin
			write_pulse = 1'b1;
			DATA_WRITE=SW;
			sm_write_state = 1;
	end
	else if (sm_write_state==1)	begin
			sm_write_state = 2;
	end
	else if(sm_write_state==2) begin
			if(WR_REQUEST_APPROVED) begin
				write_pulse = 1'b0;
				sm_write_state = 3;
			end 
	end
	else if(sm_write_state==3) begin
			if(!WR_REQUEST_APPROVED) begin
				sm_write_state = 0;
			end
	end
		
end



endmodule
